TLB & Pages
What You'll Learn
- What virtual memory and pages are
- The purpose of the TLB (Translation Lookaside Buffer)
- Why page-walks are slow
- How TLB misses affect performance
Mental Model
Programs use virtual addresses. The CPU must translate these to physical addresses to access memory. This translation is stored in page tables. The TLB caches recent translations to avoid slow page-table walks.
Virtual Memory
Programs see a virtual address space. The OS maps virtual pages to physical pages. This enables:
- Process isolation (each process has its own address space)
- Memory protection
- Swapping (pages can be moved to disk)
Pages
Memory is divided into pages (typically 4 KB on x86-64, sometimes 2 MB or 1 GB for huge pages). Each page is a contiguous block of virtual memory that maps to a contiguous block of physical memory.
TLB Purpose
The Translation Lookaside Buffer (TLB) is a small cache that stores recent virtual-to-physical page translations. It's like a cache for page table entries.
TLB hit: Translation found in TLB → fast (1 cycle)
TLB miss: Translation not in TLB → must walk page tables → slow (10-100 cycles)
Why Page-Walks Are Slow
When the TLB misses, the CPU must:
- Read page table entries from memory (multiple levels)
- Traverse the page table hierarchy
- Perform address translation
- Update the TLB with the new translation
Each page table walk requires multiple memory accesses, each with cache miss potential. This can take 10-100 cycles, depending on cache state.
TLB Capacity
TLBs are small (typically 64-512 entries for L1 TLB). If your working set spans more pages than the TLB can hold, you'll get TLB misses. This is why accessing many different pages is slow.
Checklist
- ✓ Understand virtual memory and pages
- ✓ Know what the TLB is and why it exists
- ✓ Understand why page-walks are expensive
- ✓ Ready to measure TLB effects