Gate-Level CPU Simulator

Conceptual Summary

This project implements a 32-bit single-cycle RISC CPU entirely from logic gates. Every arithmetic operation, every control signal, and every data path is constructed from fundamental boolean gates (AND, OR, NOT, XOR, NAND, NOR). There are no shortcuts—no built-in arithmetic operators used for computation, only for control flow and data structures.

The CPU follows a single-cycle architecture where each instruction completes in exactly one clock cycle. The simulation uses a two-phase clock model to properly handle sequential elements and ensure correct timing behavior.

Architecture Overview

The CPU implements a classic RISC instruction set with:

• 32-bit instruction words
• 32 general-purpose registers
• Load/store architecture
• Arithmetic and logical operations
• Branch and jump instructions

Design Philosophy

This implementation emphasizes understanding the fundamental building blocks of computation. By constructing everything from gates, we gain insight into:

• How arithmetic operations emerge from boolean logic
• The relationship between logic depth and performance
• Critical path analysis in digital circuits
• Tradeoffs between gate count and speed

Documentation Structure

Each page in this section follows a consistent structure:

• Conceptual summary: High-level explanation of the component
• Diagrams: Datapath and block diagrams showing signal flow
• Code excerpts: Key implementation details
• Performance commentary: Gate counts, critical paths, timing
• Design tradeoffs: Why certain choices were made

Writing Style

Documentation is written to be:

• Clear: Precise language, no ambiguity
• Systems-oriented: Focus on how components interact
• Concise: No fluff, only essential information
• Causal: Emphasize causality and timing relationships