“Know how to solve every problem that has been solved.” “What I cannot create, I do not understand.” — Richard Feynman

Performance Engineering

Courses

Caches, branches, vectorization — reading the machine under your code.

8 skills 0 questions ← whole tech tree

Content for this course is still being written. For now, explore the skill map below — every node links to its full page.

Skill map

Each node is a skill; an arrow means "learn this first." Deep-dive links go to the full pages.

CPU Mental Model…

A working model of modern CPU performance tradeoffs.

content coming soon
deep dive ↓Understand the CPU: Overview
Execution Model…

Pipelining and out-of-order execution.

content coming soon
deep dive ↓Execution Model
Caches…

L1/L2/L3, cache lines, temporal & spatial locality.

content coming soon
deep dive ↓Cache Overview
6502 Emulator…

Emulate an 8-bit CPU to see an instruction set run.

content coming soon
deep dive ↓6502 Emulator
Branch Prediction…

Speculation and the cost of mispredicts.

content coming soon
deep dive ↓Branch Prediction Basics
Vectorization…

SIMD: data parallelism within one core.

content coming soon
deep dive ↓SIMD / Vectorization Overview
Memory Bandwidth…

Throughput limits and how to measure them.

content coming soon
deep dive ↓Memory Bandwidth Basics
Roofline Model…

Compute-vs-bandwidth limits guide optimization.

content coming soon
deep dive ↓Roofline Model